1. Field of the Invention
The present invention relates to the field of memory chips.
2. Discussion of Related Art
A known integrated memory IC 100 that is a writeable memory of the DRAM type is shown in FIG. 1. Such a dynamic random access memory (DRAM) chip 100 includes a plurality of memory storage cells 102 in which each cell 102 has a transistor 104 and an intrinsic capacitor 106. As shown in FIGS. 2 and 3, the memory storage cells 102 are arranged in arrays 108, wherein memory storage cells 102 in each array 108 are interconnected to one another via columns of conductors 110 and rows of conductors 112. As shown in FIG. 4, the transistors 104 are used to access the capacitors 106, allowing them to charge and discharge to certain voltage levels. The capacitors 106 then store the voltages as binary bits, 1 or 0, representative of the voltage levels. The binary 1 is referred to as a “high” and the binary 0 is referred to as a “low.” The voltage value of the information stored in the capacitor 106 of a memory storage cell 102 is called the logic state of the memory storage cell 102.
As shown in FIGS. 1 and 2, the memory chip 100 includes six address input contact pins A0, A1, A2, A3, A4, A5 along its edges that are used for both the row and column addresses of the memory storage cells 102. The row address strobe (RAS) input pin receives a signal RAS that clocks the address present on the DRAM address pins A0 to A5 into the row address latches 114. Similarly, a column address strobe (CAS) input pin receives a signal CAS that clocks the address present on the DRAM address pins A0 to A5 into the column address latches 116. The memory chip 100 has data pin Din that receives data and data pin Dout that sends data out of the memory chip 100. The modes of operation of the memory chip 100, such as Read, Write and Refresh, are well known and so there is no need to discuss them for the purpose of describing the present invention.
A variation of a DRAM chip is shown in FIGS. 5 and 6. In particular, by adding a synchronous interface between the basic core DRAM operation/circuitry of a second generation DRAM and the control coming from off-chip a synchronous dynamic random access memory (SDRAM) chip 200 is formed. The SDRAM chip 200 includes a bank of memory arrays 208 wherein each array 208 includes memory storage cells 210 interconnected to one another via columns and rows of conductors.
As shown in FIGS. 5 and 6, the memory chip 200 includes twelve address input contact pins A0-A11 that are used for both the row and column addresses of the memory storage cells of the bank of memory arrays 208. In SDRAM, RAS/CAS/WE are sampled at the rising edge of the clock, its state defining the command to be executed in the CHIP. During a bank active command the address present on the DRAM address pins A0 to A11 are clocked into the bank of row address latches 214. During a READ or a WRITE command cycle, the address present on the DRAM address pins A0 to A11 are clocked into the bank of column address latches 216. The memory chip 200 has data input/output pins DQ0-15 that receive and send input signals and output signals. The input signals are relayed from the pins DQ0-15 to a data input register 218 and then to a DQM processing component 220 that includes DQM mask logic and write drivers for storing the input data in the bank of memory arrays 208. The output signals are received from a data output register 222 that received the signals from the DQM processing component 220 that includes read data latches for reading the output data out of the bank of memory arrays 208. The modes of operation of the memory chip 200, such as Read and Write, are well known and so there is no need to discuss them for the purpose of describing the present invention.
One mode of operation of a SDRAM memory chip is called Self Refresh. In this mode of operation the refreshing of the cells, either one row at a time (usually one row per refresh cycle) or groups of rows at a time, is initiated by refresh circuitry within the SDRAM memory chip that does not require intervention from the CPU or external refresh circuitry. Self-Refresh dramatically reduces power consumption and is often used in portable computers.
An example of a known Self-Refresh circuit 300 within SDRAM 200 is shown in FIG. 7. The circuit 300 includes a low frequency generator/oscillator 302, a 1:4 frequency divider 304 and a 1:32 frequency divider 306. In operation, an ENABLE signal EN is decoded by the incoming commands (or sent from the on-chip control logic), which triggers the oscillator 302 to generate a signal 308 that has a period of approximately 1 μs. The signal 308 is then fed to the 1:4 frequency divider 304 that generates a signal 310 that has a period of approximately 4 μs. The signal 310 is fed to the 1:32 frequency divider 306 where a Self-Refresh signal 312 is generated with a period of approximately 125 μs. The frequency of the Self-Refresh signal 312 is monitored on a DQ 314 pad upon entry into a test mode. Such monitoring includes sending a test mode activation signal TMSRF to the transfer gate 313 allowing the Self-Refresh signal to transfer to a DQ-Pad for monitoring. The frequency of the Self-Refresh signal 312 can be fine tuned and adjusted via trim fuses 318 and 320 associated with the oscillator 302 and the frequency divider 306, respectively.
One disadvantage of the circuit 300 is that an external measurement and hence a test mode is required to monitor the frequency of the Self-Refresh signal 312. Thus, the circuit 300 requires the use of external measuring devices that leads to an increase in costs and an increase in test time.